1. Field of the Invention
The present invention relates to a data slicer, and more particularly, to a data slicer having an error correction device.
2. Description of the Prior Art
In a general display, display frames are carried by a signal, which can be divided into vertical parts and horizontal parts. The horizontal parts represent the pixel data of each horizontal line. The vertical parts represent the display frames. The relevant standards refer to the Generalized Timing Formula (GTF) of the Video Electronics Standards Association (VESA).
To enable the display to correctly distinguish pixel data of each frame, a blanking signal is inserted between each frame. The blanking signal is composed of a front porch signal, a vertical synchronous signal, and a back porch signal. The horizontal line signals included in the front and the back porch signals are referred to as a Vertical Blanking Interval (VBI) signal. The VBI signal is utilized for transmitting control signals of frames or some data. For example, In NTSC systems, the VBI signal comprises 21 horizontal line signals, where the horizontal line signals 1 to 9 are reserved to transmit TV timing signals, and horizontal line signals 10 to 21 are reserved to transmit data signals such as teletext signals or caption signals. In PAL systems, a similar mechanism using VBI signals to transmit teletext signals and caption signals also exists.
Therefore, a general digital display has an internal VBI slicer for capturing texts, widescreen signaling signals, or VBI signals of other standards. In the prior art, the VBI slicer comprises a digital PLL and has a function of slicing level estimation. The digital PLL is utilized to lock the phase of received signals for synchronization. The function of the slicing level estimation is utilized for determining the received data as being ‘1’ by estimating if the received data is higher than a high level or as being ‘0’ by estimating if the received data is lower than a low level. However, during transmission, the amplitudes and phases of the transmitted signals are distorted because of the noises and channel effects such as thermo noise or Inter-Symbol Interference (ISI). Thus, for the digital PLL, it is hard to lock the phases of the received signals, and therefore slicing level estimation might cause incorrect determination and result in high bit-error rates.